The C9107 is an advanced IC backside polishing system for use when preparing a sample for backside failure analysis with the Phemos Series (emission microscope) or Themos Series (thermal emission monitoring system). It is used to open the package of ICs, thin the wafer substrate down to typically 50 µm and to polish the surface. Special processing tools and precedures are provided to achieve a highly precise surface quality.

A hig precision stage is used to position and move the device while processing. All operation parameters are controlled by the control program supplied with the tool. Adapting the control program to the device parameters is made by simple recipe setup.

An optional contactless micro gauge system allows measurement of the substrate thickness with a resolution better than 1 µm.

In recent semiconductor devices wiring is formed in multiple layers and components such as transistors are arranged under these metal layers. Moreover, a package structure in which a lead frame called an LOC (Lead on Chip) covers the entire surface of the chip has now come into practical use. Therefore, it has become more difficult to detect emission from the front surfaces of such semiconductor devices. Imaging from the backside of the IC has become the standart analysis method nowadays.
Backside sample preparation with highly precise surface becomes especially essential for use of Phemos systems with high resolution NanoLens optics.